An integrated voltage-mode digital to analog converter (“DAC”) consists of a network of resistors and switches. One node of the network is the output voltage and another two nodes are reference voltages. The analog output voltage is a voltage that lies somewhere between the two reference voltages as determined by a digital input code. Common designs for high accuracy voltage-mode DACs include binary weighted R2R architectures, segmented architectures that include equally weighted segments, and hybrids between the equally segmented architecture and the R2R architecture. Although these designs vary in architecture, each design provides a plurality of switchable cells that are activated based on the digital code input to the DAC. The activated cells contribute to an analog voltage generated at the DACs output. Each cell's contribution is determined, at least, in part based on the resistance of the cell itself and any coupling resistance that extends between the cell and the output terminal. Switches used in these DAC may typically be CMOS devices. The selection of CMOS devices may not be ideal however, because the CMOS devices may contain its own resistance which has an associated nonlinearity.
Moreover, the resistance associated with these CMOS switches varies according to the voltage they operate at and, since there are switches coupled to two different reference voltages, it can reasonably be expected that these will have different resistances at different switch settings. Although some attempts have been made to equalize these switch resistances to minimize this source of nonlinearity error, generally some residual error persists due to the accuracy of the method itself. Conventionally, to provide a voltage-mode DAC that is very accurate, circuit designers have opted to use large CMOS switches. Larger switches generally have a lower switch resistance, which may decrease nonlinearity error, but have the at the cost of requiring a much larger silicon area and added cost. Thus, there appears to be a need for a voltage-mode DAC design that uses smaller and more cost-effective switches. However, such a design alone may not overcome nonlinearity errors.
FIG. 1 illustrates a force/sense voltage-mode DAC as described in application Ser. No. 12/483,295. DAC 100 is an equally-weighted segmented ladder structure and is comprised of two operational amplifiers, 110 and 120 coupled to VHI and VLO at the non-inverting input. Each of the op amps 110, 120 is connected to a plurality of switch-controlled cells 130.1-130.N. For a DAC of bit width W, there would be N=2W cells. When activated, each cell 130.1-130.N contributes equally to a voltage at the voltage output.
Each cell 130.1-130.N contains two pairs of force and sense switches that are alternately closed, with one pair corresponding to nMOS devices and the other pMOS devices. Each of the switches are coupled to a resistor 140.1-140.N in the cell. The force switches (Rpf and Rnf) provide selectively conductive paths to permit either op amp to drive a given cell. When an op amp drives a particular cell, a sense switch (Rps and Rns) connected to that op amp generates a feedback path to the driving op amp.
Switching occurs between the various resistor nodes and either a high or a low reference voltage. Ideally, the voltage at the output of the voltage-mode DAC should be equal to:
                                          V            OUT                    =                                    V              LO                        +                                          D                N                            ⁢                              (                                                      V                    HI                                    -                                      V                    LO                                                  )                                                    ,                            (        i        )            where N is the total number of cells or resistor nodes, D is the input code, VHI is the high reference voltage, and VLO is the low reference voltage.
However, while the design of the force/sense voltage-mode DAC allows for rectifying the nonlinearity between MOSFET devices and the precision resistors, the DAC creates an additional nonlinearity error. In particular, a feedback path from the sense switches to the operational amplifiers introduces an additional source of nonlinearity, as a reference operational amplifier that has a non-zero input bias current introduces nonlinearity to the output of the DAC resulting in a voltage error at the output.
The voltage errors do not exist, however, at extreme values of the input code D (e.g., D is the minimum (zero) or maximum values). Therefore, the voltage error is not independent of the input code D. At D=0, all the cells are switched to the low reference voltage (“VLO”) and there is no bias current Ibp from Rps fed back to op amp 110. The contributing error at this state from sense switches RNS, is:
                                          Verr            n                    =                                                    I                bn                            ⁢                              R                ns                                                    N              -              D                                      ,                            (        ii        )            where Ibn is the biasing current to op amp 120 and RNS is the equivalent resistance of the nMOS sense switch.
At D=N, all the cells are switched to the high reference voltage and Ibn=0 and does not contribute to the error at the output. The error at the output from Ibp is:
                                          Verr            p                    =                                                    I                bp                            ⁢                              R                ps                                      D                          ,                            (        iii        )            where Ibp is the biasing current to op amp 110, and RPS is the resistance of the pMOS sense switch.
If D is between the minimum and maximum values (0<D<N), both Ibp and Ibn contribute to the error at the output. The corresponding voltage error at the output for all input codes is equal to:
                                                                        I                bn                            ⁢                              R                ns                                      N                    ,                      D            =            0                          ⁢                                  ⁢                                            V              err                        =                                                                                I                    bp                                    ⁢                                      R                    ps                                                  N                            +                                                                    I                    bn                                    ⁢                                      R                    ns                                                  N                                              ,                      0            <            D            <            N                          ⁢                                  ⁢                                                            I                bp                            ⁢                              R                ps                                      N                    ,                      D            =            N                                              (        iv        )            
As shown from equation (iv), the contribution to the voltage error at the output by Ibp and Ibn varies dependent on the interval of operation. Thus there is a need in the art, for a force/sense voltage-mode DAC that reduces nonlinearity that results from op amp input bias current from the sense switches in the DAC, by maintaining a constant error contribution at the output.